1. Field of the Invention
The present invention relates to apparatus and methods for mounting electronic compounds to a substrate. In particular, the present invention relates to a lead designed to secure jacks or sockets, which receive plug-in cables, to a printed circuit board.
2. State of the Art
As interfacing and intercommunication between independent electronic devices (personal computers, local area network severs, internet servers, personal digital assistants, digital cameras, computer peripherals, etc.) becomes commonplace, the electronics industry is striving to supplying high reliability, yet inexpensive components for interfacing such independent electronic devices. A typical interfacing device is a cable, which jacks (connects) into connectors existing on or in each of the independent electronic devices. Such connectors include, but are not limited to USB (e.g., universal serial bus), 1394 (e.g., high-speed serial bus), RJ11 (e.g., telephone jack), and RJ45 (e.g., network jack) connectors.
An inexpensive method of attaching the connectors to the internal circuitry of the independent electronic device is by surface mounting the connectors to substrates (such as print circuit boards) within the independent electronic devices. FIGS. 9-11 illustrate an exemplary surface mounted RJ45 connector assembly 200. As shown in FIGS. 9 and 10, a connector 202 is abutted against a first surface 208 of a substrate 204. Referring to FIG. 10, the connector 202 is primarily attached to the substrate first surface 208 by two relatively large (L-shaped) leads 212 and 212xe2x80x2. As shown in FIGS. 10 and 11, a portion (shown in shadow lines in FIG. 10) of each of the large leads 212 and 212xe2x80x2 extend into the connector 202, wherein they are electrically connected to routing wires (not shown) therein. Referring to FIG. 10, first portions 214 and 214xe2x80x2 of the large leads 212 and 212xe2x80x2, respectively, extend from the connector 202 abutting sides 218 and 222, respectively, of the connector 202. At the substrate first surface 208, second portions 216 and 216xe2x80x2 of the large leads 212 and 212xe2x80x2, respectively, extend substantially parallel to the substrate first surface 208. As shown in FIG. 11 (showing only large lead 212 for clarity), the large lead second portion 216 is physically and electrically attached to a landing contact 220 on or in the substrate first surface 208 with a layer of solder, such as a lead/tin alloy, forming solder joint 226. The landing contact 220 is electrically connected to traces (not shown) in or on the substrate 204.
As shown in FIG. 9, additional, smaller leads 224 may extend from the connector sides 218 and 222 (not shown for connector side 222) and electrically connected to traces (not shown) in or on the substrate 204. The large leads 212 and 212xe2x80x2 and the smaller leads 224 are the means by which electrical signals (power, ground, operational, etc.) are communicated from electronic components (not shown) mounted on the substrate 204 to the connector 202. A plug on cable (not shown) connected to an external device (not shown) is inserted into opening 206 to make electrical contact with the connector 202, whereby allowing electrical communication between an external device (not shown) and electronic components (not shown) mounted to the substrate 204.
Connectors 202 generally have cables (e.g., network interface cables for the RJ45 connector shown) connected and disconnected repeatedly over the course of the life of the connectors 202. The large leads 212 and 212xe2x80x2 are relied upon to carry stress loads resulting connecting and disconnecting of the cables. Furthermore, the connector 202 also relies upon the large leads 212 and 212xe2x80x2 to carry the stress from the coefficient of thermal expansion (CTE) mismatch between the substrate 204 and the connector 202. These stresses may cause the solder joint 226 under the large leads 212 and 212xe2x80x2 to fail (e.g., crack) due to shear stress developed in these loads.
Therefore, it would be advantageous to develop a lead design which will effectively achieve a connection of a connector to a substrate while being capable of handling the stresses induced on the connector by connecting/disconnecting cables and by CTE mismatch.